Conventionally, in a DRAM (Dynamic Random Access Memory) having a stacked capacitor, in order to compensate for a decrease of electrostatic capacitance due to a reduction in the size of the capacitor, the height of the capacitor has been increased or a high dielectric material has been used for a capacitor insulating film.
However, when the size of the capacitor further decreases in future, the above measure is not sufficient, and the configuration of the capacitor needs to be more complex. When the capacitor has a more complex configuration, a process of processing the capacitor insulating film becomes additionally necessary. For example, when a capacitor configuration in which plural capacitor layers are laminated is considered, in order to secure a connection between an upper electrode of a lower layer and an upper electrode of an upper layer and between a lower electrode of the lower layer and a lower electrode of the upper layer, respectively, it becomes necessary to perform etch back or the like on the capacitor insulating film, thereby exposing a connection part between the upper and the lower electrodes. When the capacitor insulating film is to be etched, the following problems occur.
FIG. 13A to FIG. 13C show processes of forming one capacitor layer of a capacitor having the laminated configuration.
First, as shown in FIG. 13A, an electrode film is formed on a ground interlayer insulating film 200. This electrode film is patterned to form a lower electrode 201. A capacitor insulating film 202 is formed on the whole surface including a side surface and an upper surface of the lower electrode 201. Next, the capacitor insulating film 202 is anisotropically etched, or etched back on the whole surface, to leave the capacitor insulating film on only the side wall of the lower electrode 201, as shown in FIG. 13B. As a result, the capacitor insulating film on the upper surface of the lower electrode 201 is removed. With this arrangement, a lower electrode (not shown) of the next capacitor layer to be formed on this capacitor layer can be connected to the lower electrode 201, on the exposed upper surface of the lower electrode 201.
However, due to this etch back process, an adhesion X of an etching damage, a residual molecule of an etching product, or the like occurs on the surface of the capacitor insulating film 202. This etching damage, the residual molecule, or the like increases a leakage of current between an upper electrode 203 and the lower electrode 201 as shown by an arrowhead A in FIG. 13C, thereby decreasing reliability of the capacitor.
At a lower end of the capacitor insulating film 202, there is an interface with the interlayer insulating film 200, and a connection of atom level is disconnected. Further, due to the etch back, the capacitor insulating film becomes locally thin. Consequently, leakage current occurs easily at the lower end of the capacitor insulating film 202, as shown by an arrowhead B in FIG. 13C.
Semiconductor devices having the stacked capacitors are described in, for example, Japanese Patent Application Laid-open Nos. 2000-332213, H05-267614, H11-345948, 2004-111711, and 2001-24169.